28C datasheet, 28C pdf, 28C data sheet, datasheet, data sheet, pdf, Atmel, K 32K x 8 Paged CMOS E2PROM. 28C Microchip. K (32K x 8) CMOS Electrically Erasable PROM. PIN CONFIGURATION. Top View. A 1 A7. A A *NC. Vcc. WE. [1]. A2. 5 WE. A dimensions section on page 14 of this data sheet. ORDERING INFORMATION. PLCC−32 . 28C− 28C− Units. Min. Max. Min. Max. tRC.

Author: Sazil Faezuru
Country: South Sudan
Language: English (Spanish)
Genre: Life
Published (Last): 22 February 2010
Pages: 367
PDF File Size: 16.26 Mb
ePub File Size: 3.60 Mb
ISBN: 437-4-67277-388-8
Downloads: 97636
Price: Free* [*Free Regsitration Required]
Uploader: Yozshugal

28C – 28C K ns Parallel EEPROM Technical Data

Input Test 228c256 and Measurement Level. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses refer to Software Data Protection Algorithm. OE may be delayed up to t.

A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 addi- tional bytes.

This is a stress rating only and functional operation of the device at these or any other conditions beyond those indi- cated in the operational sections of this specification is not implied.

Atmel’s 28C has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics.

28C256 – 28C256 256K 250ns Parallel EEPROM Datasheet

During a write cycle, the addresses and 1 to bytes of data are internally latched, freeing the address and data bus for other opera- tions. When CE and OE are low and WE is high, the data stored at the memory daatasheet determined by the address pins is asserted on the outputs.


Hardware and Software Data Protection. Address to Output Delay.

28C256 Datasheet PDF

Automatic Page Write Operation. CE to Output Delay. Fast Write Cycle Times.

Once a programming operation has been initiated and for the duration of t. Once the write cycle has been completed, true data is valid on all 288c256, and the next write cycle may begin.

When the device is deselected, the CMOS standby current is less than X can be V. All bytes dur- ing a page write operation must reside on the same page as defined by the state of the A6 – A14 inputs. Atmel has incorporated both hardware and software features that will protect datassheet memory against inadvertent writes.

An optional software data protection mechanism is available to guard against inad- vertent writes. PROM for device identification or tracking. The data in the enable and disable command se- quences is not written to the device and the memory ad- dresses used in the sequence may be written with data in either a byte or page write operation.

Reading the toggle bit may begin at any time during the write cycle. Stresses beyond those listed under “Absolute Maxi. If precautions are not taken, inad- vertent writes may occur during transitions of the host sys- tem power supply.


Hardware features protect against inadvertent writes to the AT28C in the follow- ing ways: Fast Read Access Time – ns. It should be noted, that once protected the host may still perform a byte or page write to the AT28C Each successive byte must be written within The address is latched on the falling edge of CE or WE, whichever occurs last.

Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer.

28C (ATMEL) – k 32k X 8 Paged Cmos E2prom | eet

Its K of memory is organized as 32, words by 8 bits. All Output Voltages with Respect to Ground The outputs are put in the high impedance state when either CE or OE is high. This is done by pre- ceding the data to be written by the dqtasheet 3-byte command sequence used to enable SDP. Once the end of a write cycle has been detected a new access for a read or write can begin.

The data is latched by dataxheet first rising edge of CE or WE.